IJSRD - International Journal for Scientific Research & Development| Vol. 3, Issue 06, 2015 | ISSN (online): 2321-0613

نویسندگان

  • Rajeev Pankaj Nelapati
  • Ravi Teja
چکیده

A CMOS class D phase locked loop based PWM generator is presented in this paper. The implementation is done in a 90nm CMOS process using CADENCE tool. The architecture in this project eliminates the requirements for a high-quality carrier generator and a high-speed voltage comparator that are often required in PWM implementations. Voltage comparison is replaced by Phase comparison and precise ramp signal is replaced by Reference clock. Phase comparison is fast and accurate when compared to voltage comparison. Reference clock does not have a stringent linearity requirement like precise ramp signal. With this we can achieve a PWM signal with 70% duty cycle.

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تاریخ انتشار 2015